1. Field of the Invention
The present invention relates to error correction circuitry and in particular to a bus comprising error correction circuitry.
2. Discussion of the Related Art
Any processing of data, including storing data or transmitting data electronically, can result in errors, and subsequent problems in regenerating the data. Error correction codes provide a means of determining when errors occur in data, and/or correcting these errors. Hamming code is an example of such an error correction code, and is based on a polarity check of various combinations of bits of a word, each combination providing one bit of error correction data.
Another example of an error correction code is described in US patent application publication US2003/0070135 developed by Laurent Murillo, which has advantages over the Hamming code in terms of usability, and generally requires one extra bit of error correction code when compared to the Hamming code.
In general, the use of error correcting codes adds a delay to the reading of data from a memory or the reception of transmitted data, which is a disadvantage.
FIG. 1 illustrates an example of a memory 100 comprising error correction code (ECC) encode block 102 and ECC decode block 104, which generate and check error coding, respectively. Thus, when writing to memory 100, data D is provided at an input 106 to the ECC encode block 102, which generates error correction bits, for example using the Hamming code mentioned above. The data D and error correction bits S are output by the ECC encode block 102 at an output 108 and are then stored in the memory cells 110 of the memory 100. When the data D is read from the memory, it is provided with associated correction bits S to the ECC decode block 104, which regenerates the error correction bits using the data from the memory cells 110, and checks that the regenerated error correction bits are the same as the stored bits S. One or more errors may be corrected by comparing the regenerated and stored error correction bits. This comparison can directly indicate the location of errors, which can be corrected by inverting the corresponding bit. The data D is then output from the ECC decode block and memory at an output 112.
In the example of FIG. 1, there is a delay in generating the error correction coding bits by block 102, and then a further delay when reading data from a memory caused by the error correction decoding block 104.
FIG. 2 illustrates an alternative example in which a microprocessor 200 on an integrated circuit (IC) 202 transmits data D to a microprocessor 204 which is part of a second IC 206. Error correction code is generated by an ECC encode block 208 on IC 202, and the data D and associated error correction code S is transmitted via a transmission line 210 to IC 206. At IC 206, an ECC decode block 212 checks the error correction code by regenerating an error correction code based on the data received via line 210, and verifies that it is the same as the code transmitted on bus 210. Again, depending on the encoding scheme used, one or more errors in the data can be detected and/or corrected. The data is then provided to microprocessor 204.
The error correction coding blocks 208 and 212 of the circuitry in FIG. 2 are also disadvantageous due to the added delay they bring to the transmission and reception of data.